1. Field of the Invention
The invention relates to data processing systems and more particularly to arbiter circuits for use in data processing systems.
2. Prior Art
Arbiters are typically used in data processing systems to resolve conflicts among data handling circuits employing shared resources such as memory units or data transfer buses in multiprocessor systems, or the like. In certain cases, the arbiter used to resolve access conflicts for resources requiring one-term access and resources requiring short-term access. By way of example in some of processor systems, all of the processors obtained access to a main memory through a common memory access circuit. The memory access circuit may include a cache memory storing a copy of information stored at certain addresses in the main memory. When one of the processors requires access to main memory, it sends a request to the memory access circuit and the memory access circuit fetches the data from its cache memory, when the information corresponding to the requested main memory address is stored in the cache. When the information corresponding to the requested main memory address is not in the cache, the memory access circuits initiate a main memory read operation. Because the main memory is typically a comparatively large memory and may be a non-volatile memory, such as a disk store having a relatively long data read times, the memory access circuitry can serve a request for data stored in its cache memory in considerably less time than when the requested data is not in cache. The case in which the data is found in cache is commonly referred to as a HIT. In the case in which the requested is not found in the cache memory, is referred to as a MISS. In the event of a MISS, the memory access circuit initiates a main memory read operation and must wait for data to be returned from main memory. The period of time between the transmission of a request and the receipt of data is referred to as a MISS window. Because the cache memory operations and the main memory operations, within the memory access circuit, are to some extent independent of each other, the memory access circuit is able to serve one or more HIT requests during a MISS window. However, such a dual operation requires the use of a dual queue.
Arbiter circuitry, including dual queues, are typically implemented in hardware since the conflicts must be resolved at a circuit level in the shortest possible real time in order to avoid undesirable delays in memory access. Furthermore, queues are preferably constructed such that they are simple to administer in order to avoid a time delay due to the administration of the queues. Additionally, the hardware queues are preferably constructed of integrated circuitry with a minimum number of circuits.
Other situations, where short-term requests and long-term requests may be handled on an overlap basis may occur in data processors using common circuitry and performing certain long-term functions, such as input/output functions for certain input/output terminals requiring long access times and other terminals requiring sufficiently shorter access times that the circuitry can be employed to perform functions with respect to different input/output terminals, on an overlap basis. In such a case, a simplified dual queue structure is highly desirable.